The invention generally concerns the manufacturing of multilayer wafer including materials selected from semiconductor materials, and used in applications in microelectronics, optics, optoelectronics and/or optonics.
More precisely, the invention concerns the processes for transferring from a “top” wafer (or donor wafer—these terms being herein understood as equivalent) a layer of a semiconductor material onto a “handle” (or receiving wafer, or “base” wafer—these terms being herein understood as equivalent) in order to make a multilayer wafer.
Several main types of such processes are known. Many of these processes imply a bonding step for bonding the handle and the top wafers, before a removal of the excess material from the bonded top wafer. We will refer to such processes which imply a bonding step as “bond and transfer processes” (or “BTP” processes).
It is specified that the definitions and corresponding acronyms givers in this document are provided for the purpose of clearly defining the invention which is the subject matter to be protected by this document. These definitional acronyms are therefore intended to be used only for the purpose of understanding this particular subject matter. They are not intended to be used for any other purpose, e.g., for the interpretation of other documents such as related patents or patent applications unless otherwise specified.
The known types of BTP processes include:
the BESOI-type process (the removal of material from the top wafer is performed through an etching of the top wafer),
the ELTRAN®-type process (the removal is performed through a detachment of the excess material with the detachment resulting from the attack of a porous region of the top wafer),
the SMART-CUT®-type process (the removal is performed through a detachment of the excess material with the detachment resulting from the splitting of the top wafer at an embrittlement or weakened region obtained by implantation of the top wafer with at least one species. It is specified that a general description of the main steps of a non-limiting embodiment of this type of method can be found in the text entitled SILICON-ON-INSULATOR TECHNOLOGY: Materials to VLSI, 2nd Edition (Jean-Pierre COLINGE).
The bonding step of such processes is generally performed without adding any adhesives (such as resins) between the top and handle wafers. We will refer to such bonding without adhesive as “direct bonding,” And a BTP comprising such a direct bonding will be referred to as “Direct bonding and transfer process” (or “DBTP”). For such direct bonding, the surfaces to be bonded must be very smooth (i.e., present a very low roughness). And it is possible to provide a smooth surface over a first wafer which is to be bonded with a second wafer through a direct bonding, e.g. by building a “bonding layer” (e.g., with an oxide layer) over the first wafer, and/or by submitting the surface of the first wafer to a specific treatment (e.g. polishing, . . . ).
A bonding of the surfaces of two wafers generates between the bonded surfaces a bonding interface associated with a given bonding energy with the higher this energy the stronger the bond. The bonding energy obtained by direct bonding two wafers without any additional treatment is sometimes not sufficiently high. This is the case in particular when it is desired to obtain with the bonding of two or more wafers a multilayer wafer (each initial wafer bringing a “layer” to the multilayer wafer thus obtained), with a high energy bond (i.e., a bonding energy typically greater than 500 mJ/m2) between the bonded wafers. In such cases, the bonded wafers are thus subjected to a “bonding heat treatment” (“BHT”) which improves bonding strength. More precisely, the BHT is generally carried out at high temperatures (i.e., at temperatures of 900° C. or higher). A high temperature BHT carried out at a temperature higher than 900° C. will be referred to herein as “HT BHT”.
A HT BHT reinforces the bonding interface and can raise its bonding energy to a desired level. As an illustration, the bonding energy between a Si wafer and a Si or SiO2 wafer is maximized after a HT BHT at temperatures on the order of 1100-1200° C. The bonding energy obtained after a HT BHT can e.g. be 2 to 2.5 J/m2 for a bonding of Si/Si, SiO2/SiO2, or Si/Si02. Such HT BHT can therefore allow the manufacturing of multilayer wafers with adequate bonding energy between the bonded layers of the wafer.
However, it can be undesirable to carry out a HT BHT on a multilayer wafer. This is the case e.g. when the layers of the multilayer wafer have respective coefficients of thermal expansion (CTE) that are significantly different. In such cases, the layers having the different CTEs will undergo expansions of different magnitudes when exposed to a HT BHT. This can lead to negative effects such as a warp of the wafers, or even the generation of defects such as dislocations in the crystalline structure of the wafers.
It can also be undesirable to carry out a HT BHT on a bonded multilayer wafer for other reasons, e.g. the wafer already comprises components totally or partially elaborated (such wafer is usually called “structured substrate”), or the material of the wafer is likely to be altered by a high temperature treatment (e.g. the case of a wafer that has a sharp doping profile with boron or phosphorous, or comprising metastable layers that would be altered by HT BHT, like low k materials, high k materials or layers with metallic elements like Al2O3, TiN, etc.).
In order to avoid such drawbacks and nevertheless obtain a high bonding energy between bonded layers of a multilayer wafer, techniques of high bonding energy at low temperatures have been developed. In one of these techniques, the surfaces to be bonded are “activated” by their exposure to a plasma, before being contacted together. Such technique will be referred to as “plasma activation” technique. Plasma activation is advantageous since it allows obtaining high bonding energy with a BHT which is carried out after contacting the surfaces to be bonded, but which remains limited to a low temperature BHT (“LT BHT”). And plasma activation has been proposed for DBTPs as a solution for obtaining a high energy bonding without requiring carrying out a HT BHT on a bonded multilayer wafer.
A general illustration of such known DBTP is given in the article entitled “Ultra-thin strained-silicon-on-insulator and SiGe-on-insulator created using low temperature wafer bonding and metastable layers”, Taraschi et al., J. Electrochem. Soc. Vol. 151, No. 1, p. 47 (2004). This article discloses a SMART-CUT®-type process in which prior to the wafer bonding step (between a top and a handle wafers) a plasma activation can be carried out on the surfaces to be bonded. The general principle of such process is illustrated in FIG. 1, which comprises FIGS. 1a to 1e to show the successive main steps of such a known principle.
FIG. 1 a shows a top wafer 10, and a handle wafer 20. The top wafer 10 has been implanted with one or more species in order to form an embrittlement or weakened zone 11. This top wafer 10 is covered by an insulator layer 12. The surface 100 of this insulator layer is to be contacted with a surface 200 of the handle wafer, for a direct bonding. These two surfaces 100, 200 shall be referred to as the respective “front” surfaces of wafers 10 and 20. And the opposite surfaces of these two wafers (respectively surface 110 and surface 210) are referred to as the respective “back” surfaces of these wafers.
FIG. 1b shows the activation of the front surfaces 100 and 200 by a plasma, in a plasma chamber. As illustrated in FIG. 1c, this activation creates an activated region 101 on the front surface 100 of the top wafer 10, and an activated region 201 on the front surface 200 of the handle wafer 20. This activation also generates contaminants due to the exposure of the wafers to a plasma. Such contaminants are more particularly illustrated by references 111 and 211 on the respective back faces 110, 210 of the wafers, as the front faces receive significantly less contaminants than the back faces (as an example, the plasma activation of a silicon wafer typically generates a contaminant concentration of about 2×1010 atoms/cm2 on the “front” surface which is to be activated and which faces the inner space of the plasma chamber, the contaminant concentration being above 1011 atoms/cm2 on the back surface of the wafer). This is due in particular to the fact that the physical contacts between each wafer and the supporting elements (e.g. chucks) associated with the plasma chamber are made on the back surface of the wafer.
In commercially available equipment for microelectronic application, the wafer is disposed on a chuck in the plasma chamber. The chuck is adapted to perform the following functions:
receive and hold the wafer very tightly in place during exposure to the plasma,
regulate the wafer temperature during plasma exposure, by temperature diffusion,
act as an electrode to transfer polarization (bias voltage) to the wafer.
This set of functions that have to be performed by the chuck leads to selecting materials for making the chuck that contain elements that are likely to contaminate the surface of the wafer in contact with the chuck (i.e. the back surface of the wafer, since it is the front surface which is directly exposed to the plasma). This material can typically be Al203 based sintered ceramics.
FIG. 1d illustrates the direct bonding of top wafer 10 and handle wafer 20, these two wafers being bonded by their front surfaces. This bonding generates a multilayer 30 wafer (also referred to as an “intermediate” multilayer wafer) which comprises in particular the embrittlement or weakened zone 11.
FIG. 1e then illustrates the multilayer wafer 35 obtained after a detachment carried out at the embrittlement zone. This wafer 35 can be a SOI (Silicon On Insulator), SGOI (Silicon-Germanium On Insulator), sSOI (strained Silicon On Insulator), GeOI (Germanium On Insulator), SiCOI (Silicon Carbide On Insulator), SOQ (Silicon On Quartz), or any other type. FIG. 1e also illustrates the remaining part of the top wafer (part 15), which has been detached. This part can be treated and reused for a new process, e.g. for constituting a new top or a new handle wafer.
This type of process illustrates that plasma activation could be advantageous for making multilayer wafers through a DBTP. But plasma activation is in itself associated with another drawback, one that is related to the contaminants generated by the activation. Indeed, as mentioned above plasma activation generates a contamination of the wafer which is exposed to the plasma, in particular on the back surface of the wafer. This “contamination” corresponds to a deposit of metallic elements (e.g. Al, Fe, Ni, Zn, Cr, Ti, Ca, Mg, Y, . . . ) that may be incorporated in fine particles, on the surface of the wafer, or absorbed in the surface in the case of isolated atoms, molecules or ions. This deposit of metallic elements can be observed with levels of contamination in the order of 5×1011 to 5×1012 atoms/cm2 on at least some areas of the surface of the exposed wafer. Such concentrations are too high for a multilayer wafer which is to be subject to further thermal treatments (e.g. a high temperature: annealing at temperatures above 1000° C. for smoothing the surface of the wafer, or further treatments carried out on the multilayer wafer for integrating 30 components into the wafer). Indeed, the contaminants of a multilayer wafer which would be exposed to such high temperatures treatments would undergo a diffusion in the volume of the wafer, and significantly alter the properties (in particular the electrical properties) of the wafer and of its components. And contaminant concentrations such as those mentioned above and resulting from a plasma activation are thus significantly higher than the specifications of maximum contamination level generally in use in the industry of manufacturing the multilayer wafers and their associated components (these specifications being in the order of 5×1010 atoms/cm2, or even less).
Thus, carrying out a direct bonding transfer process (such as e.g. a SMART-CUT®-type process) with an activation of the surfaces to be bonded as in the known state of the art, in order to make multilayer wafers, is associated with some minor drawbacks. And it is specified that if these drawbacks have been exposed hereabove in reference to a plasma activation, similar drawbacks can also be associated to the activation of a surface which is different from a plasma activation (e.g. an oxidation and/or a chemical activation, etc.). Accordingly, the present invention seeks to overcome the previously noted drawbacks and disadvantages.